The present invention relates to analog-to-digital conversion and, in particular, to a serial-parallel analog-to-digital converter with overlapping operations.
An analog-to-digital (A/D) converter encodes a voltage or current signal into a digital representation with respect to a known reference. Its accuracy is determined by the number of significant digits of the digital representation (typically the number of bits in a binary representation). The bandwidth of an A/D converter is determined by its conversion speed--the amount of time required to convert an applied input quantity to an equivalent digital representation. A widely applied class of A/D converters function by comparing an applied analog input signal to a known reference to produce a discrete or quantized signal and then encoding the quantized signal to produce a digital representation of the analog input. The particular A/D converters within this class range from what are called "serial" A/D converters in contrast to what are called "parallel" A/D converters. Serial A/D converters encode the applied analog input signal one bit at a time starting with the most significant bit and progressing sequentially towards the least significant bit. This is accomplished by coupling the analog input signal to the input of a single comparator and using control logic to couple different reference values to another input of the comparator for the conversion of each successive bit of the output representation. Thus, serial A/D converters are characterized by the advantages of relatively simple circuit configurations and low power consumption and by the disadvantage of slow conversion speeds. Parallel A/D converters, on the other hand, use a plurality of comparators each with its own distinct input reference value to allow all bits of the digital output representation to be produced simultaneously. Although the approach offers the advantage of minimum conversion time, this high speed operation is obtained only with greatly increased circuit complexity and component count. Thus, for binary output representations, N output bits would require 2.sup.N separate comparators. Many potential applications for high speed A/D converters require digital output representation of 8-bits. In applications where an A/D converter interfaces with a bus-oriented microprocessor system, an 8-bit output (which can then correspond to a computer data byte) is particularly useful. Similarly, the encoding of samples representative of a 6 megahertz color video signal requires a converter of at least 8-bits and conversion times of 80 nanoseconds or less. The implementation of an A/D converter having an 8-bit output using the parallel approach would require 256 separate comparator circuits. An A/D converter of this complexity and high component count is impractical from a cost point of view and, in particular, precludes implementation in monolithic integrated circuit form.
Another approach to A/D conversion is the serial-parallel A/D converter which is a merger of the two conversion techniques previously discussed. In converters of this type, the digital output representation is partitioned into a most significant bit (MSB) group and a least significant bit (LSB) group. Parallel conversion is used to obtain the digital output representations of both the MSB group and the LSB group but these conversions are performed in a serial fashion with the initial representation of the MSB group determining the reference voltage value required for the parallel conversion of the LSB group. Serial-parallel A/D converters yield faster conversion speeds than the all serial A/D converters with a circuit configuration which is simpler and has lower power consumption than the all parallel A/D converter.
Prior art serial-parallel A/D converters perform a conversion in the following sequence:
1. Parallel A/D conversion is used to obtain a digital representation of the MSB group; PA1 4. Parallel A/D conversion is used to convert the analog difference signal to obtain a digital representation of the LSB group.
2. Digital-to-analog conversion is used to convert the MSB representation back to a analog signal;
3. The analog representation of the MSB group is either subtracted from the input analog signal or is used to generate a change in voltage reference such that an analog difference signal is produced; and
Although the serial-parallel A/D converter represents a compromise which provides conversion speeds which are faster than exclusively serial A/D converters and which have reduced circuit complexity and component count from exclusively parallel A/D converters, the circuit delay times required in past converters of this type have made them too slow for very high speed applications such as color video encoding or interfacing with a high-speed microprocessor. Thus, it has remained a problem to obtain an effective design for an A/D converter which is simple enough in circuit configuration and low enough in component count to be implemented as a monolithic integrated circuit but which is also capable of high-speed operation.
Assignee's co-pending patent application No. 1 listed above describes one approach by which improved conversion speeds are obtained by overlapping the conversion operation required to produce a MSB and LSB group in serial-parallel A/D converter. In this approach, the active comparator output associated with MSB group conversion is used to switch the appropriate voltage reference value to the input of a voltage subtractor to obtain the analog difference signal required for LSB group conversion. In addition to the speed advantages inherent in the system configuration itself, the approach obtains improved speeds through the use of differential current switching both to obtain a high-speed latching comparator and to rapidly switch voltage reference values as required for the voltage subtraction. Although this approach works well, alternative system designs are possible which supply the reference values required for generating the analog difference signal in a different way thereby eliminating the requirement for precision differential current switches in the voltage subtractor.